High speed, low power hybrid deserializer for chiplet-to-chiplet communication

Abstract

A data conversion circuit has first cascaded flipflops, second cascaded flipflops and a first selection circuit. The first cascaded flipflops include a plurality of series-coupled dynamic flipflops configured to convert first data to second data. Each dynamic flipflop is configured to retain signaling state of its output based on a capacitance at its input. The second cascaded flipflops include a plurality of series-coupled static flipflops configured to convert the first data to the second data. Each static flipflop is configured to retain signaling state of its output through a feedback circuit that actively drives its input. The first selection circuit is configured to select between an output of the first cascaded flipflops and an output of the second cascaded flipflops to provide the second data based on frequency of a clock signal that controls a rate at which data is shifted through the data conversion circuit.