The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 2026
Filed:
Feb. 06, 2024
Applicant:
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/04 (2006.01); H02H 1/00 (2006.01); H10D 30/65 (2025.01); H10D 89/60 (2025.01);
U.S. Cl.
CPC ...
H02H 9/046 (2013.01); H02H 1/0007 (2013.01); H10D 30/65 (2025.01); H10D 89/611 (2025.01);
Abstract
The present disclosure provides a bias clamp circuit, which includes a plurality of switchable clamp voltage paths, configured to selectively clamp a gate bias voltage of a vulnerable circuit to a first voltage or a second voltage based on whether a reliability acceleration test is performed on the vulnerable circuit or not. The second voltage is higher than the first voltage.
Quick Actions:
Liu, Chien. (2026). Method for adjusting gate bias clamp voltage, semiconductor device, and bias clamp circuit using the same (U.S. Patent No. 12587010). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12587010
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile