The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Sep. 06, 2022
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Jiacen Guo, Cupertino, CA (US);

Han-Ping Chen, San Jose, CA (US);

Henry Chin, San Jose, CA (US);

Guirong Liang, Cupertino, CA (US);

Xiang Yang, Santa Clara, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/32 (2013.01); G11C 16/3427 (2013.01); G11C 16/3459 (2013.01);
Abstract

The memory device includes at least one memory block with source and drain sides and a plurality of memory cells arranged in a plurality of word lines. The word lines are arranged in a plurality of independently programmable and erasable sub-blocks. Control circuitry is configured to program the memory cells of a selected sub-block and determine a location of the within the at least one memory block and determine a programming condition of at least one unselected sub-block. The control circuitry is also configured to program at least one word line in the selected sub-block in a plurality of program loops that include pre-charging processes. The control circuitry pre-charges a plurality of channels from either the source or drain side based on at least one of the location of the selected sub-block within the memory block and the programming condition of the at least one unselected sub-block.


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