The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2026

Filed:

Jun. 03, 2024
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Marcella Carissimi, Treviolo, IT;

Marco Pasotti, Travaco′ Siccomario, IT;

Riccardo Zurla, Binasco, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G06F 7/544 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0028 (2013.01); G11C 13/0004 (2013.01); G11C 13/0061 (2013.01); G06F 7/5443 (2013.01);
Abstract

An in-memory computation device performs a multiply-and-accumulate (MAC) operation. A computation array includes groups of memory cells coupled to a bitline, each group storing a computational weight and having a positive cell flowing a positive-cell current and a negative cell flowing a negative-cell current which are a function of a total current and the sign and absolute value of the respective computational weight. A row-activation circuit receives an input signal and provides, for each input value, during an elaboration interval, a positive-activation signal having a positive-activation duration and a negative-activation signal having a negative-activation duration, the durations being a function of an elaboration duration and of the sign and absolute value of the respective input value. A column-elaboration circuit samples bitline current and provides, in response thereto, at least one output signal.


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