Multiplexing scheme for multi-clock prototyping

Abstract

Aspects of the present disclosure address systems and methods for multi-clock prototyping. Data representing an integrated circuit design is accessed. The integrated circuit design comprises multiple partitions and specifies a set of cut nets between a first partition and a second partition. A plurality of clock domains among the set of cut nets is identified. A clock domain comprises a subset of cut nets from the set of cut nets. A multiplexer/demultiplexer pair is assigned to each clock domain. Bandwidth allocations for the plurality of clock domains are computed. The bandwidth allocation for a given clock domain corresponds to a number of links between the first partition and the second partition allocated to a multiplexer/demultiplexer pair assigned to the clock domain. A prototype of the integrated circuit design is implemented based on the bandwidth allocations.