The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Aug. 11, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Ke-Jing Yu, Kaohsiung, TW;

Yu-Chen Chang, Taoyuan, TW;

Anhao Cheng, Taichung, TW;

Yen-Liang Lin, Tainan, TW;

Ru-Shang Hsiao, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2025.01); H01L 21/321 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H01L 21/28123 (2013.01); H01L 21/3212 (2013.01); H10D 84/0172 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01);
Abstract

A semiconductor structure includes a substrate with fin features extending along a first direction; a plurality of gate stacks and a plurality of dummy pillars. The gate stacks are deposited over the substrate and extend along a second direction different from the first direction to cover the sidewalls and top surfaces of the fin features exposed from the substrate. Each gate stack includes a first gate region, a second gate region and a central region formed between the first gate region and the second gate region without covering the fin features. The dummy pillars are formed in the gate stacks besides the fin features and/or on the fin features.


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