The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2026
Filed:
Oct. 14, 2022
Applicant:
Globalfoundries U.s. Inc., Malta, NY (US);
Inventor:
Shesh Mani Pandey, Saratoga Springs, NY (US);
Assignee:
GlobalFoundries U.S. Inc., Malta, NY (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/65 (2025.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H10D 30/657 (2025.01); H01L 21/76267 (2013.01); H01L 21/76283 (2013.01); H10D 30/0281 (2025.01); H10D 64/01 (2025.01); H10D 64/254 (2025.01); H10D 64/258 (2025.01);
Abstract
A semiconductor device comprises a semiconductor layer over an insulator layer and a base layer under the insulator layer. A well is in the base layer, a doped region is above and coupled with the well, and the doped region is in the insulator layer. A drift region is above and coupled with the doped region, and the drift region is at least partially in the semiconductor layer. A gate stack is partially over the semiconductor layer and partially over drift region.
Pandey, Shesh. (2026). Metal oxide semiconductor devices and integration methods (U.S. Patent No. 12581686). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12581686
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile