The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

Jul. 28, 2023
Applicant:

Shanghai Huali Microelectronics Corporation, Shanghai, CN;

Inventors:

Tianquan Shi, Shanghai, CN;

Zhenghong Liu, Shanghai, CN;

Ruisheng Qi, Shanghai, CN;

Haoyu Chen, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H10B 43/35 (2023.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10D 30/0413 (2025.01); H10B 43/35 (2023.02); H10D 30/022 (2025.01); H10D 30/69 (2025.01); H10D 64/015 (2025.01);
Abstract

A method for manufacturing a SONOS memory discloses forming first a thin oxide layer as a sidewall protection layer and a blocking layer. This layer prevents the high dielectric-constant layer at the bottom of the stacked gate structure from being exposed on the surface. An lightly doped drain (LDD) implantation area is defined by a lateral thickness of a thin oxide layer, so that the channel width may be controlled by controlling the thickness of the thin oxide layer. Thus, the width of a current channel at the bottom of a gate is reduced under the same ion implantation condition into the active area, thereby improving a current capacity of the SONOS memory without adding any mask or photolithography step, and thus bring no additional patterning costs or active area ion implantation costs.


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