The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

May. 27, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yongseok Kwon, Seoul, KR;

Youngsik Rho, Changwon-si, KR;

Sangwon Park, Seoul, KR;

Sungwhan Seo, Hwaseong-si, KR;

Dongkyu Lee, Hwaseong-si, KR;

Jaeyong Jeong, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/00 (2006.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01); H10B 63/00 (2023.01); H10D 1/40 (2025.01);
U.S. Cl.
CPC ...
H10D 1/40 (2025.01); H01L 24/80 (2013.01); H01L 25/18 (2013.01); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/40 (2023.02); H10B 63/34 (2023.02); H10B 63/845 (2023.02); H01L 2225/06541 (2013.01);
Abstract

A memory device including a first substrate extending in a first direction and a second direction perpendicular to the first direction, the first substrate including a memory cell region and a first peripheral circuit region, and a second substrate, including a second peripheral circuit region, extending in the first and second direction, the second substrate overlapping the first substrate in a third direction perpendicular to the first and second direction. The memory device also including a memory cell array disposed in the memory cell region and including a plurality of vertical channel structures extending in the third direction, a peripheral circuit disposed in the second peripheral circuit region, and a resistor extending in the third direction through the first peripheral circuit region and the second peripheral circuit region. The resistor including a plurality of resistance contact structures overlapping the plurality of vertical channel structures in the first direction.


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