Memory cell, memory and method for manufacturing memory

Abstract

A memory cell includes a transistor, a storage node contact and a capacitor that are connected sequentially, wherein the capacitor includes a lower electrode, an upper electrode and a dielectric layer disposed between the lower electrode and the upper electrode. The lower electrode includes: a first electrode layer having a first sub-electrode region and a plurality of second sub-electrode regions connected to the first sub-electrode region, where the first sub-electrode region is in contact with a surface of the storage node contact, each of the second sub-electrode regions extends along a direction away from the storage node contact and has a first end face and a second end face facing each other in an extension direction, the first end face being in contact with the surface of the storage node contact; and a second electrode layer, covering at least part of a surface of the first electrode layer.