Generation of random security circuit patterns for in-situ fabrication of tamper-respondent sensors

Abstract

In-situ fabrication of tamper-respondent sensors with random security circuit patterns is provided. The method includes establishing a random security circuit pattern for fabricating a security circuit of a tamper-respondent sensor to enclose, at least in part, one or more components within a secure volume. The establishing includes generating a trace pattern extending once through nodes of a plurality of nodes dispersed within an area of the tamper-respondent sensor, and randomly modifying the trace pattern to produce a randomly modified trace pattern with a desired randomization index relative to a specified randomization threshold, and providing the randomly modified trace pattern as a random security circuit pattern. Further, the method includes initiating fabricating of the tamper-respondent sensor in-situ on a surface of an enclosure to facilitate defining the secure volume, with the fabricating using the random security circuit pattern.