The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2026

Filed:

May. 16, 2024
Applicant:

Peking University, Beijing, CN;

Inventors:

Yimao Cai, Beijing, CN;

Zongwei Wang, Beijing, CN;

Yunfan Yang, Beijing, CN;

Ru Huang, Beijing, CN;

Assignee:

PEKING UNIVERSITY, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 7/106 (2013.01); G11C 7/1063 (2013.01); G11C 7/12 (2013.01);
Abstract

A compute-in-memory circuit based on charge redistribution includes a memory array, multiple-functional output units (MFUs), multiplexers (MUXs), and a word line (WL) driver. The memory array includes memory cell rows and memory cell columns. Every two adjacent memory cells form a memory cell pair in sequence, and every two adjacent memory cell columns form a memory cell column pair in sequence. A grounded register capacitor is connected to a source line (SL) of each memory cell row. Input ends of each MFU are connected to a first bit line (BL) and a second BL of each memory cell column pair, respectively. Each MUX includes voltage-input ends and an output end, and the output end of each MUX is connected to the SL of each memory cell row in a one-to-one correspondence. An output end of the WL driver is connected to a WL of each memory cell row.


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