Programmatically generated reduced fault injections for functional safety circuits

Abstract

Techniques are disclosed for eliminating redundancy in fault simulations to improve efficiency and to reduce the time and computing power required to generate a robust fault list, which results in adequate diagnostic coverage of a particular post-silicon electronic device for functional safety applications. The techniques described herein implement an automated methodology to identify identical sub-circuits in a design after the design is synthesized to gates, and utilize isomorphism to define a manner in which identical blocks may be reliably identified to ensure adequate coverage and accurate, consistent fault injection results. The netlist may advantageously implement a 'flat' as opposed to a hierarchal design. Moreover, multiple levels of granularity may be identified for the various sub-circuits associated with the reference graphs used to identify isomorphic sub-graphs.