Memory device, memory system, memory controller, and operation method

Abstract

Examples of the present disclosure include a memory device including: a memory cell array including a plurality of blocks. The blocks include a plurality of word lines, and a plurality of memory cells coupled to the plurality of word lines. The plurality of memory cells coupled to a same word line form a physical page. A physical page includes one or more code words; and a peripheral circuit coupled to the memory cell array and configured to: acquire a predicted initial read voltage of the one or more code words according to a position of the word line coupled to the one or more code words in an open block and a position of a first blank physical page in the open block; and obtain a target valley voltage of the code words according to a first result corresponding to the code words at the predicted initial read voltage.