The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Jun. 26, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Wen-Ju Chen, New Taipei City, TW;

Chung-Ting Ko, Kaohsiung City, TW;

Wan-Chen Hsieh, Hsinchu, TW;

Chun-Ming Lung, Hsinchu, TW;

Tai-Chun Huang, Hsinchu, TW;

Chi On Chui, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/311 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H01L 21/3085 (2013.01); H01L 21/0234 (2013.01); H01L 21/02348 (2013.01); H01L 21/02356 (2013.01); H01L 21/02521 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 21/3065 (2013.01); H01L 21/3086 (2013.01); H01L 21/31111 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/021 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0184 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract

A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.


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