The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Jun. 11, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chun-Yao Ku, Hsinchu, TW;

Wen-Hao Chen, Hsinchu, TW;

Kuan-Ting Chen, Hsinchu, TW;

Ming-Tao Yu, Hsinchu, TW;

Jyun-Hao Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/20 (2020.01); G06F 30/392 (2020.01); H01L 23/538 (2006.01); H10D 89/10 (2025.01); H10K 30/83 (2023.01);
U.S. Cl.
CPC ...
H10D 89/10 (2025.01); G06F 30/20 (2020.01); G06F 30/392 (2020.01); H01L 23/5386 (2013.01); H01L 23/5387 (2013.01); H10K 30/83 (2023.02);
Abstract

An integrated circuit includes a first region of the integrated circuit including a first set of pins extending in a first direction, being on a first level, and having a first width in a second direction different from the first direction. The first region has a first height in the second direction. An integrated circuit further includes a second region of the integrated circuit adjacent to the first region, the second region including a second set of pins extending in the first direction, being on a first level, being separated from the first set of pins in the second direction, and having a second width in the second direction, the first width being different from the second width. The second region has a second height in the second direction different from the first height, and the first level is a first metal layer of the integrated circuit.


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