The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2026
Filed:
Jun. 04, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Jo-Chun Hung, Hsinchu City, TW;
Chih-Wei Lee, Taipei City, TW;
Wen-Hung Huang, Hsin-Chu, TW;
Hui-Chi Chen, Hsinchu County, TW;
Jian-Hao Chen, Hsinchu City, TW;
Kuo-Feng Yu, Hsinchu County, TW;
Hsin-Han Tsai, Hsinchu, TW;
Yin-Chuan Chuang, Yunlin County, TW;
Yu-Ling Cheng, Tainan City, TW;
Yu-Xuan Wang, New Taipei City, TW;
Tefu Yeh, Kaohsiung City, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A sacrificial layer is formed over a first channel structure of an N-type transistor (NFET) and over a second channel structure of a P-type transistor (PFET). A PFET patterning process is performed at least in part by etching away the sacrificial layer in the PFET while protecting the NFET from being etched. After the PFET patterning process has been performed, a P-type work function (WF) metal layer is deposited in both the NFET and the PFET. An NFET patterning process is performed at least in part by etching away the P-type WF metal layer and the sacrificial layer in the NFET while protecting the PFET from being etched. After the NFET patterning process has been performed, an N-type WF metal layer is deposited in both the NFET and the PFET.