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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12575147 B1

PDFFull Text
Date of Patent:
Mar. 10, 2026

Filed:

May. 09, 2023

3d-stacked transistor structure with barrier layer between upper gate structure and lower gate structure

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jaejik Baek, Watervliet, NY (US);

Seungchan Yun, Waterford, NY (US);

Kang-Ill Seo, Springfield, VA (US);

Assignee:

SAMSUNG ELECTRONICS CO., LTD., , KR;

Attorney:

Myers Bigel, P.A.

Primary Examiner:

Christine A Enad

Int. Cl.
CPC ...
H10D 62/10 (2025.01); H01L 25/07 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H01L 25/074 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 84/0167 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01);
Abstract

Provided is a three-dimensionally-stacked field-effect transistor (3DSFET) device including a plurality of 3DSFETs on a single substrate, wherein each of the 3DSFET includes: a 1channel structure surrounded by a 1gate structure; and a 2channel structure surrounded by a 2gate structure, the 2channel structure provided on the 1channel structure, and wherein, in at least one of the 3DSFETs, the 1gate structure is isolated from the 2gate structure through a barrier layer including a dielectric material comprising tantalum.

Find Patent Forward Citations

Baek, Jaejik. (2026). 3d-stacked transistor structure with barrier layer between upper gate structure and lower gate structure (U.S. Patent No. 12575147). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12575147

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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