The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2026
Filed:
Jul. 24, 2023
Wenzhou University, Zhejiang, CN;
Hao Ye, Zhejiang, CN;
Pengjun Wang, Zhejiang, CN;
Bo Chen, Zhejiang, CN;
Yijian Shi, Zhejiang, CN;
Gang Li, Zhejiang, CN;
Jialin Jiang, Zhejiang, CN;
Haoran Fang, Zhejiang, CN;
Xiaolong Yu, Zhejiang, CN;
Wenzhou University, Zhejiang, CN;
Abstract
A FET with a multi-value switching function comprises a source region, a channel region, a drain region, a gate dielectric layer, a substrate layer, a gate-oxide inducer layer, a metal layer and a spacer layer. The channel region is an undoped channel region, the drain region is an undoped drain region. The metal layer comprises first to third metal blocks which are arranged at intervals from left to right, the distance between the first metal block and the second metal block is 12 nm, the distance between the second metal block and the third metal block is 10 nm, the first metal block is a main control gate of the FET, the second metal block and the third metal block are two inducer gates of the FET, and the spacer layer is used for isolating the first metal block from the second metal block and the third metal block.