The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Apr. 14, 2021
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventor:

Kazunari Nakata, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/66 (2025.01); H02M 1/08 (2006.01); H10D 12/01 (2025.01); H10D 62/17 (2025.01); H10D 62/832 (2025.01); H10D 64/27 (2025.01); H02M 7/5387 (2007.01); H02P 27/08 (2006.01);
U.S. Cl.
CPC ...
H10D 30/668 (2025.01); H02M 1/08 (2013.01); H10D 12/031 (2025.01); H10D 62/393 (2025.01); H10D 62/8325 (2025.01); H10D 64/518 (2025.01); H02M 7/53871 (2013.01); H02P 27/08 (2013.01);
Abstract

An object of the present disclosure is to provide a trench gate type power semiconductor device that does not easily break even when stress is applied. A SiC-MOSFET includes a SiC substrate, a drift layer of a first conductive type, formed on the SiC substrate, a base region of a second conductivity type formed in a surface layer of the drift layer, a source region of the first conductivity type selectively formed in a surface layer of the base region, a trench extending through the base region and the source region and reaching the drift layer, a gate electrode embedded in the trench and having a V-shaped groove on an upper surface thereof, and an oxide film formed on an upper surface including the groove of the gate electrode, in which a bottom of the V-shape groove is deeper than the base region.


Find Patent Forward Citations

Nakata, Kazunari. (2026). Power semiconductor device with gate having v-groove upper surface and method of manufacturing thereof (U.S. Patent No. 12575131). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12575131

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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