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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12575116 B1

PDFFull Text
Date of Patent:
Mar. 10, 2026

Filed:

Jul. 25, 2023

Integrated memory and control dies

Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Srinivasan Sivaram, Los Gatos, CA (US);

Jayavel Pachamuthu, San Jose, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:

PEARL COHEN ZEDEK LATZER BARATZ LLP

Primary Examiner:

Viet Q Nguyen

Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 11/00 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); G11C 11/005 (2013.01); H01L 24/08 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1443 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A memory system comprises a monolithic integration of a NAND die, a MRAM die and one or more control dies positioned in a same semiconductor package for high speed and high density non-volatile data storage. The MRAM die can be operated as a cache for the NAND die or to provide long term data storage for data not cached for the NAND die. In one embodiment, the NAND die comprises a plurality of NAND strings. The MRAM die comprises a MRAM structure. The one or more control dies comprise one or more control circuits for operating the NAND die and the MRAM die.

Find Patent Forward Citations

Sivaram, Srinivasan. (2026). Integrated memory and control dies (U.S. Patent No. 12575116). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12575116

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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