The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2026
Filed:
Apr. 23, 2021
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Yun-Yan Chung, Hsinchu, TW;
Chao-Ching Cheng, Hsinchu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/30 (2023.01); H01L 21/02 (2006.01); H10B 43/30 (2023.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 48/36 (2025.01); H10D 62/80 (2025.01); H10D 64/68 (2025.01); H10D 99/00 (2025.01);
U.S. Cl.
CPC ...
H10B 51/30 (2023.02); H01L 21/02565 (2013.01); H01L 21/02568 (2013.01); H10B 43/30 (2023.02); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 30/69 (2025.01); H10D 30/701 (2025.01); H10D 48/362 (2025.01); H10D 62/80 (2025.01); H10D 64/685 (2025.01); H10D 64/689 (2025.01); H10D 64/693 (2025.01); H10D 99/00 (2025.01);
Abstract
A memory device includes a transistor and a memory cell. The transistor includes a first gate electrode, a second gate electrode, a channel layer, and a gate dielectric layer. The second gate electrode is over the first gate electrode. The channel layer is located between the first gate electrode and the second gate electrode. The gate dielectric layer is located between the channel layer and the second gate electrode. The memory cell is sandwiched between the first gate electrode and the channel layer.