The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Jan. 29, 2024
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Hieu Van Tran, San Jose, CA (US);

Andrew Kunil Choe, San Jose, CA (US);

Hoa Vu, Milpitas, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 3/00 (2006.01); G06F 17/16 (2006.01); H03M 1/46 (2006.01);
U.S. Cl.
CPC ...
H03M 3/464 (2013.01); G06F 17/16 (2013.01); H03M 1/466 (2013.01);
Abstract

In one example, a system comprises a vector-by-matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns; and a sigma-delta analog-to-digital converter to receive a current from a column of the vector-by-matrix multiplication array and to generate a digital output in response to the current.


Find Patent Forward Citations

Tran, Hieu. (2026). Sigma-delta analog-to-digital converter to generate digital output from vector-by-matrix multiplication array (U.S. Patent No. 12574048). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12574048

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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