The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Jan. 09, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Daniele Vimercati, El Dorado Hills, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 7/10 (2006.01); G11C 7/18 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/1039 (2013.01); G11C 7/18 (2013.01);
Abstract

Methods, systems, and devices for signal development circuitry layouts in a memory device are described. A memory device may include signal development circuitry that is positioned in multiple levels of a memory die relative to a substrate. For example, a set of first transistors used for developing access signals may be located on a first level of a memory die, and a set of second transistors used for developing the access signals may be located on a second level of the memory die. Formation of the set of first transistors and the set of second transistors may involve processing operations that are common with the formation of other transistors on a respective level, such as cell selection transistors, deck selection transistors, shunting transistors, and other transistors of the respective level.


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Vimercati, Daniele. (2026). Signal development circuitry layouts in a memory device (U.S. Patent No. 12573436). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12573436

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