The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 2026

Filed:

Jun. 16, 2022
Applicant:

Siemens Industry Software Inc., Plano, TX (US);

Inventors:

Sridhar Srinivasan, Tualatin, OR (US);

Yi-Ting Lee, Zhubei City, TW;

Lei Ling, Fremont, CA (US);

Chung Lee, Tigard, OR (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/367 (2020.01); G06F 21/71 (2013.01); G06F 30/398 (2020.01); G06F 119/10 (2020.01);
U.S. Cl.
CPC ...
G06F 21/71 (2013.01); G06F 30/367 (2020.01); G06F 30/398 (2020.01); G06F 2119/10 (2020.01);
Abstract

This application discloses a computing system implementing a reliability verification tool to identify a portion of a layout design describing an integrated circuit includes a victim transistor having a gate connected to an aggressor transistor. The reliability verification tool can extract a resistance network for connections between the victim transistor and the aggressor transistor, and simulate the resistive network to determine connectivity between the wells of the victim transistor and the aggressor transistor occurs prior to the victim transistor having a gate connected to an aggressor transistor.


Find Patent Forward Citations

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Srinivasan, Sridhar. (2026). Path-based layer stack connectivity check for plasma induced damage avoidance (U.S. Patent No. 12572701). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12572701

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