Memory with improved incomplete active performance loss task completion detection

Abstract

Memory systems and devices (and associated methods) with improved active performance loss (APL) completion detection are described herein. In one embodiment, a memory device comprises nonvolatile memory and logic configured to (i) write a first value to a first location in the nonvolatile memory, (ii) detect a power loss event corresponding to the memory device, and (iii) before powering down the memory device based at least in part on the detected power loss event, write a second value to a second location in the nonvolatile memory different from the first location. The first value and/or the second value can correspond to a current power cycle number of the memory device. After power is subsequently restored to the memory device, the logic can compare the first and second values and proceed with reconstructing the memory device using APL management data when the first value matches the second value.