Processor and method for executing a looping code segment with zero overhead

Abstract

Example processors and methods for executing a looping code segment with zero overhead are provided. An example processor includes a pipelined architecture configured to execute a looping code segment having a first loop instruction at a first loop instruction address, a last loop instruction at a last loop instruction address, and a loop branch instruction. The processor includes a branch target address predictor, having a branch identifier, first instruction operational codes associated with the first loop instruction, a second loop instruction address in sequence with the first loop instruction address, and a branch taken indicator indicating a likelihood that the loop branch instruction directs execution to the first loop instruction. The branch target address predictor enables the pipelined architecture to execute the looping code segment with zero overhead, meaning the last loop instruction and the first loop instruction are executed on consecutive cycles.