Back-end-of-line cmos inverter having twin channels and one gate electrode and methods of forming the same

Abstract

An embodiment inverter circuit includes a first-conductivity-type semiconductor layer disposed over an interlayer dielectric layer, a gate electrode disposed over the first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer disposed over the gate electrode, a first gate dielectric layer disposed between the first-conductivity-type semiconductor layer and the gate electrode, a second gate dielectric layer disposed between the gate electrode and the second-conductivity-type semiconductor layer, a first source electrode that is in contact with the first-conductivity-type semiconductor layer, a second source electrode that is in contact with the second-conductivity-type semiconductor layer, and a shared drain electrode that is in contact with the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. At least one of the first-conductivity-type layer and the second-conductivity-type layer includes a metal-oxide semiconductor and/or a multi-layer structure formed in a BEOL process that may be incorporated with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices.