The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 03, 2026

Filed:

Jul. 27, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventor:

Katherine H. Chiang, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/14 (2006.01); G11C 29/00 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 29/14 (2013.01); G11C 29/44 (2013.01); G11C 29/702 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01);
Abstract

Various embodiments of the present disclosure are directed towards a method for memory repair using a lookup table (LUT)-free dynamic memory allocation process. An array of memory cells having a plurality of rows and a plurality of columns is provided. Further, each memory cell of the array has multiple data states and a permanent state. One or more abnormal memory cells is/are identified in a row of the array and, in response to identifying an abnormal memory cell, the abnormal memory cell is set to the permanent state. The abnormal memory cells include failed memory cells and, in some embodiments, tail memory cells having marginal performance. During a read or write operation on the row, the one or more abnormal memory cells is/are identified by the permanent state and data is read from or written to a remainder of the memory cells while excluding the abnormal memory cell(s).


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