The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

May. 02, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Hsiang-Tai Lu, Hsinchu County, TW;

Kuan-Lung Wu, Hsinchu County, TW;

Yu-Wei Chiu, Pingtung County, TW;

Wen-Chien Chang, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/52 (2006.01); H01L 23/64 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/642 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 2224/16221 (2013.01); H01L 2924/1431 (2013.01);
Abstract

A semiconductor structure includes a core layer; a passive component disposed within the core layer; and a first redistribution layer disposed over the core layer, wherein the first redistribution layer includes a first interconnect, a second interconnect, and a third interconnect disposed between and electrically isolated from the first interconnect and the second interconnect. The third interconnect is electrically connected to the passive component, and at least one of the first interconnect and the second interconnect is electrically isolated from the passive component. A method of manufacturing the semiconductor structure includes providing a first bias between the first interconnect and the second interconnect, providing a second bias to the passive component through the third interconnect, wherein the first bias is greater than the second bias.


Find Patent Forward Citations

Lu, Hsiang-Tai. (2026). Semiconductor structure having passive component and method of manufacturing thereof (U.S. Patent No. 12564066). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12564066

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…