The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2026
Filed:
Apr. 27, 2023
Applicant:
Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;
Inventors:
Yu-Ting Tsai, New Taipei, TW;
Chung-Liang Cheng, Changhua County, TW;
Ching-Jing Wu, Zaoqiao Township, TW;
Chyi-Tsong Ni, Hsin-Chu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76843 (2013.01); H01L 21/76805 (2013.01); H01L 21/76876 (2013.01); H01L 21/76895 (2013.01); H01L 23/53266 (2013.01); H01L 23/535 (2013.01);
Abstract
A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.
Tsai, Yu-Ting. (2026). Semiconductor arrangement and method of making (U.S. Patent No. 12564024). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12564024
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile