The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2026
Filed:
May. 04, 2023
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Chih Feng Sung, Hsinchu, TW;
Wei Han Huang, Hsinchu, TW;
Ming-Jui Tsai, Hsinchu, TW;
Yu Chi Chen, Hsinchu, TW;
Yung-Hsiang Chang, Hsinchu, TW;
Chun-Lin Lu, Hsinchu, TW;
Shih-Ping Lee, Hsinchu, TW;
Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;
Abstract
A wafer stacking method includes the following steps. A first wafer is provided. A second wafer is bonded to the first wafer to form a first wafer stack structure. A first edge defect inspection is performed on the first wafer stack structure to find a first edge defect and measure a first distance in a radial direction between an edge of the first wafer stack structure and an end of the first edge defect away from the edge of the first wafer stack structure. A first trimming process with a range of a first width is performed from the edge of the first wafer stack structure to remove the first edge defect. Herein, the first width is greater than or equal to the first distance.