The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

Jan. 24, 2022
Applicant:

Ferroelectric Memory Gmbh, Dresden, DE;

Inventor:

Stefano Sivero, Comun Nuovo, IT;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/134 (2014.01); G11C 7/00 (2006.01); G11C 8/00 (2006.01); G11C 16/00 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/134 (2014.07); G11C 7/00 (2013.01); G11C 8/00 (2013.01); G11C 16/00 (2013.01); H03K 2005/00019 (2013.01); H03K 2005/00195 (2013.01);
Abstract

Disclosed herein is a programmable delay circuit for providing an adjustable delay for a signal transmitted from an input node to an output node. The adjustable delay circuit includes an input node; an output node; and a pair of inverter circuits coupled in series between the input node and the output node, wherein the pair of inverter circuits is configured to provide an adjustable delay for a signal transmitted from the input node to the output node. At least one inverter circuit of the pair of inverter circuits includes a state-programmable memory element that allows the pair of inverter circuits to be configurable between a first delay mode or a second delay mode.


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