The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 24, 2026

Filed:

May. 06, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kuljit S. Bains, Olympia, WA (US);

Jongwon Lee, Portland, OR (US);

Tomer Levy, Tel Aviv, IL;

Bill Nale, Livermore, CA (US);

Amir Ali Radjai, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/406 (2006.01); G11C 11/4078 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 11/40615 (2013.01); G11C 11/40622 (2013.01); G11C 11/4078 (2013.01); G11C 11/4096 (2013.01);
Abstract

Methods and apparatus for row hammer (RH) mitigation and recovery. A host comprising a memory controller is configured to interface with one or more DRAM devices, such as DRAM DIMMs. The memory controller includes host-side RH mitigation logic and the DRAM devices include DRAM-side RH mitigation logic that cooperates with the host-side RH mitigation logic to perform RH mitigation and/or recovery operations in response to detection of RH attacks. The memory controller and DRAM device are configured to support an RH polling mode under which the memory controller periodically polls for RH attack detection indicia on the DRAM device that is toggled when the DRAM device detects an RH attack. The memory controller and DRAM device may also be configured to support an RH ALERT_n mode under which the use of an ALERT_n signal and pin is used to provide an alert to the memory controller to initiate RH mitigation and/or recovery.


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