Extraction based on heterogeneous meshing techniques

Abstract

A software tool used to assess and/or simulate an integrated circuit ('IC') layout employs heterogeneous resistance extraction and/or meshing, to combine advantages of a relatively compact parasitics file size and robustness for effective simulation and electrical performance analysis. In one embodiment, filters are automatically applied (or are manually specified by a user) to select structures, layers, geographic regions, nets or other areas of a design which will receive additional extraction and/or meshing scrutiny, with the remainder of the design being subjected to default practices. For example, software can be scripted (or rule driven) to perform 1D meshing for in-layer electrical pathways while providing 2D, 3D, or other complex meshing for vias, contact pads, device instances, selected nets and/or other structures. Techniques can be applied for reassessing impact of structural redesign, and reports and/or visualization can be generated, each enhanced by the use of heterogeneous meshing.