Bit error detection in a compute-in-memory system, method of operating same, and method of manufacturing same

Abstract

A compute-in-memory memory (CIM) system includes: in a first region of a semiconductor die, first components including memory cells correspondingly configured to store single bits, and arrays including multipliers and first bit-error detectors; first ones of the memory cells being arranged in corresponding first arrays and being configured to store first bits; second ones of the memory cells being arranged in corresponding second arrays and being configured to store parity bits corresponding to the first bits; and for first groups each of which including a corresponding one of the first arrays, the second arrays, the multipliers and the first bit-error detectors, the multiplier being configured to perform a multiplication of input bits and corresponding ones of the first bits, and the first bit-error detector being configured to perform a detection of a bit-error in the corresponding first bits based on the corresponding parity bits.