The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Jun. 16, 2023
Applicant:

Hefechip Corporation Limited, Hong Kong, CN;

Inventors:

Chih Yuan Lee, Taoyuan, TW;

Hong-Hui Hsu, Zhubei, TW;

Yiheng Xu, Clifton Park, NY (US);

Laertis Economikos, Wappingers Falls, NY (US);

Chao-Hsu Chang, Ballston Lake, NY (US);

Wei-Chuan Chen, Scarsdale, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 50/01 (2023.01); H10B 61/00 (2023.01); H10N 50/20 (2023.01); H10N 50/80 (2023.01);
U.S. Cl.
CPC ...
H10N 50/01 (2023.02); H10B 61/00 (2023.02); H10N 50/20 (2023.02); H10N 50/80 (2023.02);
Abstract

A method for fabricating an MRAM device is disclosed. The method includes: depositing a first dielectric layer and a second dielectric layer over a semiconductor substrate; depositing a bottom electrode layer over the second dielectric layer, and forming an MTJ stack and a hard mask layer over the bottom electrode layer; patterning the hard mask layer and forming at least one MTJ pillar by etching the MTJ stack with the patterned hard mask layer serving as a mask; depositing a first ILD layer over a top surface of the hard mask layer and on sidewalls of the hard mask layer and MTJ pillar; performing a first etch-back process on the first ILD layer, such that a surface of the first ILD layer on each side of the hard mask layer and the MTJ pillar forms a slope of 40°-70° with respect to a surface of the semiconductor substrate.


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