The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Jun. 06, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Kisik Choi, Watervliet, NY (US);

Chanro Park, Clifton Park, NY (US);

Shogo Mochizuki, Mechanicville, NY (US);

Tenko Yamashita, Schenectady, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H01L 21/76897 (2013.01); H01L 23/5286 (2013.01); H01L 23/535 (2013.01); H10D 30/014 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01);
Abstract

Aspects of the present invention provide a semiconductor structure. The semiconductor structure may include a PFET source/drain (S/D). The PFET S/D may include a silicon germanium (SiGe)-based epi protruding through a BILD plane between a backside interlayer dielectric (BILD) and a first gate, and an NFET S/D. The NFET S/D may include a silicon (Si)-based epi protruding into the BILD plane and a SiGe epi between the BILD and the Si-based.


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