Enhancement mode transistor with a robust gate and method

Abstract

A disclosed structure includes an enhancement mode high electron mobility transistor (HEMT). The HEMT includes a barrier layer with a thick portion positioned laterally between thin portions and a gate. The gate includes a semiconductor layer (e.g., a P-type III-V semiconductor layer) on the thick portion of the barrier layer and having a thick portion positioned laterally between thin portions. The gate also includes a gate conductor layer on and narrower than the thick portion of the semiconductor layer, so end walls of the gate are stepped. Thin portions of the barrier layer near these end walls minimize or eliminate charge build up in a channel layer below. To block current paths around the gate, isolation regions can be below the thin portions of the barrier layer offset from the semiconductor layer. The structure can further include alternating e-mode and d-mode HEMTs. Also disclosed are associated method embodiments.