The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Jan. 17, 2023
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Ling-Yi Chuang, Hefei, CN;

Kaimin Lv, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 80/00 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H10B 80/00 (2023.02); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/05017 (2013.01); H01L 2224/05018 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/48235 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01);
Abstract

Embodiments provide a fabricating method, a semiconductor structure, and a semiconductor device. The method includes: providing a plurality of chips, each of the chips includes an element region and a scribe line region arranged in a first direction; stacking the chips to form a chip module, where a stacking direction of the chips is a second direction perpendicular to the first direction, the element regions of the chips are overlapped with each other, and the scribe line regions of the chips are overlapped with each other; planarizing a side surface of each of the scribe line regions distant from the element region after the chip module is formed, to remove at least part of the scribe line regions and expose the power supply wiring layer; and forming a pad on the side surface planarized, where the pad is connected to the power supply wiring layer.


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