The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2026
Filed:
Aug. 17, 2023
Micron Technology, Inc., Boise, ID (US);
Ching-Huang Lu, Fremont, CA (US);
Vinh Quang Diep, Hayward, CA (US);
Avinash Rajagiri, Boise, ID (US);
Yingda Dong, Los Altos, CA (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. During the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line. During the subset of erase loops, a first adjusted erase bias voltage is caused to be applied to the first select gate and a second adjusted erase bias voltage is caused to be applied to the second select gate.