Memory device having cache storage unit for storage of current and next data pages and program operation thereof

Abstract

A memory device includes an array of memory cells in columns and rows, word lines respectively coupled to rows, bit lines respectively coupled to the columns, bit lines respectively coupled to the columns of the memory cells, and a peripheral circuit coupled to the array of memory cells through the bit lines and the word lines and configured to program a select row based on a current data page. Each peripheral circuit includes page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit configured to, in programming a select memory cell of the select row to one of 2levels based on the current data page, store one of N bits of the current data page and one of N bits of a next data page in a time division manner.