The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Dec. 21, 2023
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Zhichao Du, Wuhan, CN;

Xuesong Shen, Wuhan, CN;

Daesik Song, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H10B 80/00 (2023.02); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01);
Abstract

Decoder circuit, memory device, and control method are disclosed. The decoder circuit includes a decoding circuit and a power supply control circuit including: a first transistor, its input is connected to a low-level voltage node, and its output outputs a first ground voltage; a second transistor, its input is connected to a high-level voltage node, and its output outputs a first voltage; and a reverse circuit, its input receives a semiconductor component enabling signal, and its output is connected to the control terminal of one of the first or second transistor; and the control terminal of the first or second transistor not connected to the reverse circuit receives the semiconductor component enabling signal. The decoding circuit includes sub-circuits, wherein a power supply interface of sub-circuit is connected to the output of second transistor, or a grounding interface of sub-circuit is connected to the output of first transistor.


Find Patent Forward Citations

Du, Zhichao. (2026). Decoder circuits, memory devices and its control method (U.S. Patent No. 12555624). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12555624

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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