The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2026

Filed:

Jul. 27, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Channappa Desai, Haveri, IN;

Derek Yang, Poway, CA (US);

Sunil Sharma, Bangalore, IN;

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4078 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4078 (2013.01); G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01);
Abstract

A replica column for bit line tracking of a bitcell array is disclosed that includes just one replica access transistor for each row in the bitcell array. If there are N rows, there are thus N replica access transistors in the replica column, where N is a plural positive integer. The replica column includes no other transistors besides the replica access transistors.


Find Patent Forward Citations

Desai, Channappa. (2026). Memory with one-transistor-based bit line tracking circuit (U.S. Patent No. 12555622). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12555622

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…