The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 17, 2026
Filed:
Apr. 01, 2022
Intel Corporation, Santa Clara, CA (US);
Neelam Chandwani, Portland, OR (US);
Shridhar Bendi, Bangalore, IN;
Rajesh Vivekanandham, Bangalore, IN;
Rahul Pal, Bangalore, IN;
Eric J. Dahlen, Portland, OR (US);
Antonio J. Hasbun Marin, San Antonio de Belen, CR;
Chung-Chi Wang, Sunnyvale, CA (US);
Qian Li, Beaverton, OR (US);
Hosein Nikopour, San Jose, CA (US);
Sravanthi Kota Venkata, San Jose, CA (US);
Rajesh Poornachandran, Portland, OR (US);
Udayan Mukherjee, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.