The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Aug. 13, 2021
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Xuefeng Hua, Foster City, CA (US);

Jack Chen, San Francisco, CA (US);

Ian Scot Latchford, Palo Alto, CA (US);

Chia-Shin Lin, Taipei, TW;

Chanthavisa Keovisai, San Jose, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/321 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02021 (2013.01); H01L 21/02019 (2013.01); H01L 21/02164 (2013.01); H01L 21/02274 (2013.01); H01L 21/3212 (2013.01); H01L 22/12 (2013.01);
Abstract

Semiconductor processing methods and apparatuses are provided. Some methods include providing a first wafer to a processing chamber, the first wafer having a thickness, a beveled edge, a first side, and a plurality of devices formed in a device area on the first side, the device area having an outer perimeter, depositing an annular ring of material on the first wafer, the annular ring of material covering a region of the beveled edge and the outer perimeter of the device area, and having an inner boundary closer to the center point of the first wafer than the outer perimeter, bonding a second substrate to the plurality of devices and to a portion of the annular ring of material, and thinning the thickness of the first wafer.


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