The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Jul. 31, 2023
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Tao Li, Slingerlands, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Kisik Choi, Watervliet, NY (US);

John Christopher Arnold, North Chatham, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H01L 21/762 (2006.01); H01L 23/528 (2006.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 30/0198 (2025.01); H01L 21/76224 (2013.01); H01L 23/5286 (2013.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0151 (2025.01); H10D 84/832 (2025.01);
Abstract

Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming a passive device area and a logic device area on a substrate; forming a diffusion break between the passive device area and the logic device area, wherein the diffusion break extends into the substrate; removing a portion of the substrate to expose a bottom portion of the diffusion break; covering a first portion of the substrate underneath the passive device area and the bottom portion of the diffusion break with a hard mask; selectively removing a second portion of the substrate to expose at least a portion of a bottom surface of the logic device area; and depositing a backside interlevel dielectric (BILD) layer to cover the portion of the bottom surface of the logic device area. The semiconductor structure formed thereby is also provided.


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