The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Jun. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Raghunandan Makaram, Northborough, MA (US);

Kirk S. Yap, Westborough, MA (US);

Rajat Agarwal, Portland, OR (US);

George Vergis, Portland, OR (US);

Bill Nale, Livermore, CA (US);

Jacob Doweck, Haifa, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G11C 29/12 (2006.01); G11C 29/42 (2006.01); H04L 9/06 (2006.01); H04L 9/08 (2006.01); H04L 9/32 (2006.01);
U.S. Cl.
CPC ...
H04L 9/0631 (2013.01); G11C 29/12015 (2013.01); G11C 29/42 (2013.01); H04L 9/0637 (2013.01); H04L 9/0838 (2013.01); H04L 9/3242 (2013.01);
Abstract

A memory subsystem includes link encryption for the system memory data bus. The memory controller can provide encryption for data at rest and link protection. The memory controller can optionally provide link encryption. Thus, the system can provide link protection for the data in transit. The memory module can include a link decryption engine that can decrypt link encryption if it is used, and performs a link integrity check with a link integrity tag associated with the link protection. The memory devices can then store the encrypted protected data and ECC data from the link decryption engine after link protection verification.


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