Memory controller and operation method thereof, and memory system

Abstract

Implementations of the present disclosure disclose a memory controller and an operation method thereof, and a memory system. The operation method of the memory controller can include a starting step of entering a high-order error correction mode when the data read from a memory block belongs to correctable error correction code data and an error bit count of the memory block is greater than a specific value, a detection step of checking whether an inducement type of the error bit count is charge leakage, and a remedying step of complementarily applying programming pulse signals to the memory block if the inducement type is the charge leakage. The present application reduces the refresh probability of the memory block, reduces the write amplification factor, and thus extends the service life of the memory device.