The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2026

Filed:

Nov. 22, 2023
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Tetsuo Fukushi, Tokyo, JP;

Hiroyuki Takahashi, Tokyo, JP;

Muneaki Matsushige, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4096 (2006.01); G11C 11/4072 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 11/4072 (2013.01); G11C 11/408 (2013.01); G11C 11/4093 (2013.01);
Abstract

A current consumption in a DRAM circuit is reduced. The DRAM circuit is a dynamic random access memory (DRAM) circuit provided with a main input/output line pair and a reset circuit. A potential of the main input/output line pair is held in a period from an end of a write cycle to a start of a first write cycle after the write cycle or a period from the end of the write cycle to a start of a first read cycle after the write cycle. The reset circuit resets a state of the main input/output line pair at a time of the start of the first read cycle.


Find Patent Forward Citations

Fukushi, Tetsuo. (2026). Dram circuit (U.S. Patent No. 12548617). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12548617

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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